1. Field of the Invention
This invention relates to a test structure for multi-layer thin-film modules, and more particularly to a test structure located in one or more corner chip site regions to provide production monitoring, yield prediction, and reliability testing.
2. Description of the Prior Art
A typical thin-film, multi-chip carrier has many thick-film ceramic layers, indicated by the reference numeral 12, and a number of thin-film wiring layers.
The wiring layers can be sequentially formed or formed independently using a parallel process and brought together to form the multi-layer structure. The purpose of the entire thin-film module is to provide interconnections, power, and cooling to integrated circuit chips that are mounted on the top surface of the module. The thin-film wiring layers 14 are typically organized such that one layer contains electrical conductors running in one given direction (e.g., an X direction) while another layer contains wires running in a direction perpendicular to the first layer (e.g., a Y direction). The conductors of the two layers are interconnected by an interleaving via layer having conductors extending vertically through the layer. Disposed on one or both sides of the X-Y plane pair is a reference plane or mash layer having, for example, a grid of conductors disposed thereon. The module may contain one or more of such X-Y plane pairs and further via layers. The conductors within the various layers may be formed by any of a number of suitable thin-film fabrication techniques such as, for example, a photolithographic technique.
While the processing of the thin-film module is conceptually somewhat similar to the metal (i.e., personalization) processing of an integrated circuit chip with many metal levels, between chip sites on a thin-film module there is no free area similar to the KERF on a semiconductor wafer. The manufacturing of an I.C. chip can be monitored by placing defect test structures in the KERF area, which is an area unusable for active devices as it is consumed in dicing the chips. In addition, several full chip sites with yield test structures are placed on the wafer to maintain yield. These reduce the chip productivity but do not reduce the chip density. Using a full chip test site on thin-film module would result in reduction of the number of product chips per module and also block some of the wiring channels.
There have been proposals in the prior art for process monitors for thin-film wiring modules. U.S. Pat. No. 4,933,635 to Deutsch et al., and assigned to the assignee of this application, discloses a thin-film, multi-layer module with fabrication process and tooling monitors for monitoring the quality of the fabrication process during the sequential formation of the layers in the thin-film region. The process monitor is formed along with a desired layer or layers of the thin-film region, such as by a photolithographic process. The fabrication monitor sites are located around the periphery of the central active wiring regions; the sites can be located such that they do not occupy or interfere with the surface area required for the wiring regions while still being disposed near enough to the wiring regions such that the electrical and physical characteristics of the thin-film monitor are substantially the same as the active wiring region. This perimeter region represents, however, the non-uniform edge region of the polyimide film with higher defect density then the central region and thus is unsuitable for lithography. Four different types of thin-film fabrication thin-film monitors are disclosed, including a line/via monitor, a dielectric monitor, a laser-assisted repair monitor and a laser-assisted engineering change monitor.
The monitoring of the processing, yield, performance and reliability of this film module represents an unsolved problem since there is absolutely no space on the thin-film module to be used to place test structures. Immediately outside the chip site area on the thin-film module, the polyimide perimeter (a module edge area 20 and a seal area 22 shown in FIG. 2) cannot be used because it is unsuitable for lithography. There is no possibility to provide even a narrow area on the thin-film module between the chip sites and polyimide perimeter for a monitoring test site or test sites. The maximum active area is determined by the ceramic substrate technology. This technology limits the maximum ceramic active substrate area usable for the thin-film module. The chip and chip site are designed in such a way that every micron of this active area is used to increase circuit density.